blind buried hole plate

1. Design codes and core challenges
Blind Buried Hole Design Rules
Hole diameter and depth-to-diameter ratio:
Blind hole: laser drilled hole diameter ≥ 0.1mm, depth-to-diameter ratio ≤ 1:1 (e.g. 0.1mm hole diameter / 0.1mm depth).
Buried hole: mechanically drilled hole diameter ≥ 0.2mm, depth-to-diameter ratio ≤ 10:1 (e.g. 0.3mm hole diameter corresponds to 3mm laminate thickness).
Spacing requirements:
Hole edge to wire spacing ≥ 0.15mm, spacing between holes ≥ 0.2mm, to avoid plating short circuit.
Impedance control:
The capacitance introduced by blind holes needs to be compensated by simulation (e.g. HFSS optimization) to ensure impedance tolerance ±8%.
Lamination optimization strategy
Sequential lamination method:
Layer by layer lamination (e.g., L2-L5, then L1 and L6-L8) to reduce interlayer stress.
Stacked Via vs. Staggered Via:
Stacked Via saves space but increases process difficulty; Staggered Via improves reliability but occupies more area.

2. Material selection and process key points
Substrate Material Requirements
High Tg material: Tg≥170℃ (e.g. Isola FR408HR), able to withstand high temperature (180~200℃) for multiple pressing.
Low CTE matching: Z-axis CTE ≤ 50 ppm/°C to prevent hole copper fracture after lamination (e.g. Panasonic MEGTRON6).
Core process steps
Laser drilling:
CO2 laser (for non-metallic materials) or UV laser (metal + medium), accuracy ±15μm.
Hole wall roughness Ra <1μm, plasma cleaning required to remove carbonized residues.
Electroplated hole filling:
Blind holes are filled with copper (conductive paste) or resin plugged holes, surface flatness ＜10μm.
Buried holes need to be plated before lamination to ensure that the copper thickness in the holes is ≥20μm.
Lamination alignment:
Use X-ray alignment system, interlayer offset ≤25μm, to avoid blind hole misalignment leading to open circuit.

3. Typical application scenarios and design cases
Smartphone motherboard (10-layer arbitrary layer HDI)
Blind holes: L1-L2 and L9-L10, hole diameter 0.1mm, copper filling to ensure flatness.
Buried holes: L3-L8 interlayer buried holes, hole diameter 0.2mm, staggered to reduce crosstalk.
High-speed server CPU slots
Blind vias: L1-L3 short stubs (Stub <0.1mm) to reduce signal reflection.
Buried hole: L4-L6 interlayer differential pair hopping, hole spacing 0.3mm, impedance 100Ω±5%.