HDI Board

1. Material characterization requirements
Low dielectric constant (Dk) with low loss factor (Df)
High frequency applications (e.g., 5G, millimeter wave) require low Dk/Df materials (e.g., Panasonic MEGTRON, Rogers RO4000 series) to minimize signal delay and loss.
Example: Dk value needs to be stabilized below 3.5 and Df value below 0.005@10GHz.
High Glass Transition Temperature (Tg)
Lead-free soldering process requires Tg ≥ 170°C (e.g. FR-4 High Tg) to avoid high temperature delamination.
Coefficient of Thermal Expansion (CTE) Matching
Z-axis CTE needs to be close to copper layer (14-18 ppm/°C) to prevent hole wall fracture after multiple reflow soldering.
Interlayer Interconnect Technology
Microvia structure
Blind/buried holes ≤150μm in diameter (commonly used laser drilling), depth to diameter ratio ≤1:1, e.g. 0.1mm hole diameter / 0.1mm depth. Stacked Vias or Staggered Vias to optimize signal path.
Plated Vias Filling (Via Filling)
Filling with copper fill or conductive/non-conductive paste to ensure a flat surface to support fine pitch BGA packages.
3. Line Design Specifications
Fine line width/spacing
Line width/spacing ≤3mil (75μm), high order HDI up to 1.5mil (38μm), need to be combined with etching compensation.
Impedance control: ±10% tolerance, stacking optimization through simulation tools (e.g. Polar Si9000) is required.
Any Layer HDI (Any Layer Interconnect)
The whole layer uses laser holes to realize more than 10 layers of arbitrary interlayer connection, and the wiring density is increased by more than 50%.
4. Surface treatment process
Leveling and Reliability
Electroless Nickel-Palladium (ENEPIG): Suitable for ultra-fine pitch components (e.g., 0.35mm pitch BGA) with high oxidation resistance.
Immersion Silver (Immersion Silver): low cost, but need anti-sulfur treatment; OSP is suitable for short cycle assembly.
5. Manufacturing process key points
Laser drilling precision
UV laser precision ±15μm, CO2 laser for large aperture, need to control the hole wall roughness (Ra <1μm).
Lamination alignment
Layer alignment error ≤25μm, calibrated by X-ray alignment system.
Plating uniformity
Pulse plating ensures that the copper thickness in the hole is ≥20μm to avoid the “Dog-bone effect”.
6. Reliability Test Standards
Thermal stress test
IPC-TM-650 2.6.8: 5 times 288℃ solder heat resistance test (no delamination).
Resistance change <10% after 1000 times -40℃~125℃ thermal cycling (TCT).
Mechanical Reliability
Drop test (e.g. JEDEC JESD22-B111): 30 times 1m drop without breakage.
Bending test (for flexible HDI): dynamic bending >1000 times (radius 3mm).
7. Typical application scenario optimization
Consumer electronics (e.g. cell phones)
Adopt any layer of HDI (more than 10 layers), line width/spacing 2/2mil, with Via-in-Pad design.
Automotive electronics
High temperature resistant material (Tg≥180℃), AEC-Q100 certified, stricter CTE control.
High Frequency Communication
Hybrid dielectric layer (e.g. FR-4+Rogers material), combined with grounded via array to suppress signal crosstalk.